ParaEst: A Machine Learning-based Parasitic Capacitance Estimation Tool

The ParaEst project was an intern research project I conducted at the Integrated Circuit (IC) Lab in Huawei Canada as part of an emerging initiative to apply machine learning to the IC design process. The project initially began as a research experiment, where we showed that machine learning methods such as a Support Vector Regressor (SVR) were able to estimate parasitic capacitances between transistors given the netlist of an IC schematic design. Typically, designers need to transform their schematic designs into a layout design in order to obtain accurate values for parasitic capacitances. Then, a designer would annotate their schematics with the parasitic capacitances obtained from layout design simulations and re-annotate the schematics to verify that circuit specifications are still being met. Typically, many iterations between schematic and layout design would be required until adequate performance is reached. However, by applying machine learning prior to layout design, designers could use the estimated parasitics to gain a more accurate understanding of their circuits performance and reduce the number of design iterations.

With a trained machine learning model, the next step was to incorporate the ML core into a tool that was intuitive for designers to use. Through weekly feedback sessions with senior designers, I identified the key design requirements that were necessary in the tool. Incorporating their comments, I was able to build a PyQt application from scratch with native support for Cadence Virtuoso CAD software, which the designers use to design their circuits. The predicted parasitic capacitances were used in various features, such as auto-annotation of schematics, comparison of existing estimates and ML predictions, and toggling between designer and ML capacitance annotations. Near the end of the internship, the tool was handed off to designers for experimental validation on their next generation of IC designs.